`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:17:02 04/02/2014 
// Design Name: 
// Module Name:    keyDecoder 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module keyDecoder(keyRel, keyCode, keyFlag, enter, up, down, left, right, shoot, bomb, reset);

input keyRel;   // indicates that the next key code received should be released
input keyFlag;  // indicates new keycode is ready to be evaluated
		
input [7:0] keyCode;  // 8 bit code obtained from key press

output reg enter, up, down, left, right, shoot, bomb, reset; // game control signals
	
		reg rel; // signal to release a key
		
	initial begin   // initialize all signals to zero
		rel <= 1'b0;
		enter <= 1'b0;
		up <= 1'b0;
		down <= 1'b0;
		left <= 1'b0;
		right <= 1'b0;
		shoot <= 1'b0;
		bomb <= 1'b0;
		reset <=1'b0;
	end

always @ (negedge keyFlag) begin  // whenever a new keycode is received

	if (keyRel) begin  // set the release signal
		rel <= 1'b1;
	end

	else begin
		if (rel) begin  // release the given key
			case (keyCode)  
				8'h5A: enter <= 1'b0; //enter key
				8'h75: up <= 1'b0;	//up	
				8'h72: down <= 1'b0; //down
				8'h6B: left <= 1'b0;	 //left
				8'h74: right <= 1'b0; //right
				8'h14: shoot <= 1'b0; //left ctrl key
				8'h29: bomb <= 1'b0;	//space bar
				8'h2D: reset <=1'b0; //'r' key
				default: ;
			endcase
			rel <= 1'b0;	 // reset release signal
		end
		
		else begin  // press the given key
			case (keyCode)  
				8'h5A: enter <= 1'b1; //enter key
				8'h75: up <= 1'b1;		//up arrow	
				8'h72: down <= 1'b1;	//down arrow
				8'h6B: left <= 1'b1;	//left arrow
				8'h74: right <= 1'b1;	//right arrow
				8'h14: shoot <= 1'b1; //left ctrl key
				8'h29: bomb <= 1'b1;	//space bar
				8'h2D: reset <=1'b1; //'r' key
				default: ;
			endcase				
		end		
	end

end

endmodule

